Integrated circuits in microelectronic devices are becoming smaller in order to provide higher performance for products requiring advanced technology. The integrated circuits are comprised of several layers which are individually formed with a unique pattern. The pattern is transferred from a reticle or mask into a photoresist layer on a substrate during a lithography process. The pattern is then transferred from the photoresist layer into an underlying substrate usually by means of an etching step. After the photoresist is removed, a pattern remains in the substrate and consists of trenches, via holes, lines, or other features that form pathways for electrical connections within and between layers. Generally, before a new layer can be formed above an existing one, the topography must be planarized to enable a uniform layer of photoresist to be coated on top of it. This can occur by coating a planarizing organic anti-reflective layer before the photoresist film is formed or by using a chemical mechanical polish (CMP) to form a smooth surface on the substrate.
In certain layers, shallow trench isolation (STI) structures are needed to separate areas where active devices are to be formed. The process typically involves forming a trench between areas where active devices will be located, filling the trench in a high density plasma (HDP) chemical vapor deposition (CVD) process with a dielectric material and employing CMP to smooth the surface. Dielectric materials such as silicon dioxide insulate active devices from one another and thereby prevent crosstalk between wiring which would have a detrimental impact on device performance.
The STI structure has been used to fabricate state of the art devices with minimum feature sizes in the range of 130 nm to 250 nm (0.13 to 0.25 microns). As shown in FIG. 1, a shallow trench 20 consists of an opening in an etch stop layer such as silicon nitride layer 12 and extends into an underlying substrate 10. The dimensions of the trench 20 are a width x and a height y that define an aspect ratio of y/x which is usually in the range of about 4.3 to about 5.6. The thickness of the silicon nitride layer 12 is typically from about 1600 Angstroms to about 2000 Angstroms and the height of the shallow trench 20 is generally from about 5600 Angstroms to about 6000 Angstroms. Optionally, there may be a silicon oxide layer between the silicon nitride and the substrate. Once the shallow trench 20 is filled with a dielectric material, it will be useful in isolating active areas from one another. These active areas will be formed in subsequent process steps.
A gap fill process normally involves a high density plasma (HDP) chemical vapor deposition (CVD) of a dielectric material such as silicon dioxide. For example, silane (SiH4) and oxygen can be combined in an HDP CVD process to form silicon dioxide. Referring to FIG. 2, a shallow trench 20 has been previously formed within a silicon nitride layer 12 and a substrate 10. FIG. 2 illustrates a prior art process in which the gas mixture used for the deposition contains argon. As a result of the argon flow, the rate of sputtering is high and sidewall deposition is enhanced which increases the probability of keyhole or void formation in the dielectric layer 14. A keyhole 16 is likely to form near the bottom of the shallow trench 20. If not corrected, the keyhole 16 will remain in the STI structure and cause a loss of performance in the resulting microelectronic device. Therefore, an improved method that avoids keyhole formation in the bottom half of the STI structure and is able to easily remove those formed in the top half of a trench is needed.
Current HDP CVD processes can only completely fill trenches with x >0.17 microns and an aspect ratio <3. Besides feature sizes of 0.13 to 0.18 microns required for current technologies in manufacturing, new devices that will reach manufacturing in the near future need trench widths with dimensions of 0.10 micron or smaller. In the case of STI features, as the width x of the trench becomes ≦0.13 micron, the aspect ratio may increase in some applications to ≧4.3. This specification will make the fabrication of STI structures especially difficult because of a high probability of forming voids or pinhole defects within the dielectric material as it is deposited.
Because of the increasing cost of manufacturing tools including those containing HDP CVD chambers and plasma etch chambers, it is imperative that the number of processing steps be minimized when fabricating a device. A simpler process translates into reduced cost per device and a more attractively priced product in the marketplace. It is also desirable to extend the lifetime of existing equipment to the manufacture of new generations of technology. While HDP CVD tools have been developed with a new design that may be capable of generating STI structures with gap spaces of ≦0.13 micron width and aspect ratio of ≧4.3, implementing them in a production line would have a significant impact in driving up the cost of the product.
Some of the STI trenches are densely packed where the distance between trenches is approximately the same as the width of the trench itself. Other trenches are essentially isolated and have no adjacent trenches within about 1 micron. When densely packed and isolated trenches occur on the same layer, it is desirable to be able to perform the HDP CVD and etch steps so that all STI trenches are filled simultaneously and completely.
The deposition of the dielectric material to fill the trench occurs at high temperature and may result in stress within the structure in addition to the voids or pinhole defects. Several methods to overcome these problems exist in the prior art. U.S. Pat. No. 6,306,722 describes a method to dope the silicon dioxide dielectric fill material which allows the deposition temperature to be reduced and thereby relieve stress in the structure. However, this method does not claim applicability to features as small as 0.13 micron with high aspect ratios or address the problem of pinhole formation within the trench. U.S. Pat. No. 6,261,957 mentions the use of a sputter etch method to help planarize the dielectric material above the trench prior to the CMP process but does not address a solution to the void formation problem during the deposition itself. U.S. Pat. No. 6,297,128 describes a method to alleviate the stress in the dielectric film but requires up to 25 layers to be deposited which would have a large impact on manufacturing cost.
U.S. Pat. No. 5,182,221 describes an electron cyclotron resonance (ECR) CVD process that deposits two types of dielectric material in three steps. However, this method does not mention aspect ratios greater than 3. There is no evidence that it would function as an effective gap fill process for shallow trenches smaller than 0.20 to 0.25 microns. Moreover, ECR CVD tools are not commonly used in manufacturing because of a lower throughput and high cost of ownership.